The increasing demand for seamless integration of high-voltage components, such as batteries (3-5 V), with low-voltage Si complementary metal-oxide-semiconductor (CMOS) devices (≤ 1.8 V) represents a challenge in modern electronic systems. A promising solution is the implementation of high-voltage thin-film transistors (TFTs) in the back-end-of-line (BEOL) of CMOS chips. BEOL high-voltage TFTs would enable direct integration with low-voltage front-end-of-line (FEOL) transistors, facilitating energy efficient and compact systems. Amorphous gallium oxide (a-GaOx) emerges as a promising channel material for these TFTs due to its wide bandgap (~4.9 eV) and low deposition temperature, critical for BEOL compatibility. In this work, we study a-GaOx TFTs fabricated using plasma-enhanced atomic layer deposition (PE ALD). We explore the tunability of a-GaOx thin film properties by changing the O2 plasma conditions, the optimization of device performance, and the integration of top-gated TFTs on BEOL CMOS chips. We demonstrate that a-GaOx electrical properties can be precisely controlled by PE-ALD by decreasing the O2 plasma exposure time during ALD cycles at a low deposition temperature of 250°C. The films transition from insulating at long plasma times (≥ 8 s) to semiconducting at shorter plasma times (≤ 3 s), without requiring additional doping or annealing. Back-gated a-GaOx TFTs exhibit excellent performance metrics, including a threshold voltage (Vt) of 4.5 V, a subthreshold slope (SS) of 200 mV/dec, an ON/OFF ratio of 106, and a current density of 50 nA/µm for device dimensions of L= 6 µm and W = 10 µm. The devices show a hysteresis effect between forward and reverse voltage sweeps, with a hysteresis window of 4-5 V in the pristine state down to 1 2 V for the third measurement. We show that in-situ Al2O3 encapsulation of the a-GaOx channel significantly reduces the hysteresis, down to 2.7 V in the pristine state and down to 0.7 V in subsequent measurements. However, further optimization of the encapsulated devices is required as encapsulation led to a degradation of the transistor properties. Alternatively, we utilize the observed hysteresis effect to demonstrate its potential for charge-trap memory devices. We demonstrate a difference in program and erase state currents of over one order of magnitude and a retention larger than 102 s. By applying sequential erase pulses we achieve nine distinct memory states. Optimizing metal-semiconductor interfaces also proves crucial, with Ti emerging as the most effective contact material among the metals tested (W, Al, Ti, Ni and Ta), likely due to the formation of a TiOx interface layer between Ti and a-GaOx. We show that post-fabrication annealing in N2 atmosphere for 3 min at 400°C of the Ti-based devices further improves the device performance, achieving a Vt of 1 Abstract 4.4 V, a SS of 250 mV/dec, an ON/OFF ratio of 106 and a current density of 20 nA/µm, for device dimensions of L = 1 µm and W = 50 µm. Finally, we realize the integration of top-gated a-GaOx TFTs in the BEOL of CMOS chips, marking a significant milestone in demonstrating the compatibility of our a-GaOx and our processes with advanced semiconductor technologies. We achieve devices with a Vt of 1.7 V, a SS of 570 mV/dec, an ON/OFF ratio of 104 and a current density of 0.12 nA/µm, for device dimensions of L = 5 µm and W = 30 µm. We evidence that the fabrication of the a-GaOx TFTs has some impact on the FEOL transistor properties, which originates from the O2 plasma during a-GaOx deposition. The findings of this study highlight the potential of a-GaOx as a promising material for thin film transistors, addressing challenges such as hysteresis, contact resistance and integration compatibility. Our work establishes a strong foundation for the further development of a-GaOx thin film transistors for 3D integration in nanoelectronics.
